High-speed serial data streams are often transmitted to a receiver without an accompanying clock signal. The receiver needs an appropriate clock to sample and recover data from the stream. In a process commonly known as clock and data recovery (CDR), the receiver can generate the needed clock from an approximate frequency reference, and then phase-align the clock to the center point between data transitions (i.e., a 0 to 1 or 1 to 0). The data stream can then be sampled using the phase-aligned clock. In this manner, the receiver can recover the true content of the input data stream notwithstanding a lack of an accompanying clock signal.